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INTEGRATED CIRCUITS
NE570 Compandor
Product data Supersedes data of 1990 Jun 07 2003 Apr 03
Philips Semiconductors
Philips Semiconductors
Product data
Compandor
NE570
GENERAL DESCRIPTION
The NE570 is a versatile low cost dual gain control circuit in which either channel may be used as a dynamic range compressor or expandor. Each channel has a full-wave rectifier to detect the average value of the signal, a linerarized temperature-compensated variable gain cell, and an operational amplifier. The NE570 is well suited for use in cellular radio and radio communications systems, modems, telephone, and satellite broadcast/receive audio systems.
PIN CONFIGURATION
RECT_CAP_1 RECT_IN_1 G_CELL_IN_1 GND INV_IN_1 RES_R3_1
1 2 3 4 5 6 7 8 TOP VIEW
16 15 14 13
RECT_CAP_2 RECT_IN_2 G_CELL_IN_2 VCC INV_IN_2 RES_R3_2 OUTPUT_2 THD_TRIM_2
NE570D
12 11 10 9
FEATURES
OUTPUT_1 THD_TRIM_1
* Complete compressor and expandor in one IC * Temperature compensated * Greater than 110 dB dynamic range * Operates down to 6 VDC * System levels adjustable with external components * Distortion may be trimmed out
APPLICATIONS
SR02503
Figure 1. Pin configuration.
* Cellular radio * Telephone trunk comandor * High level limiter * Low level expandor--noise gate * Dynamic noise reduction systems * Voltage-controlled amplifier * Dynamic filters
ORDERING INFORMATION
Type number Package Name NE570D SO16 Description plastic small outline package; 16 leads; body width 7.5 mm Version SOT162-1 0 C to +70 C Temperature range
BLOCK DIAGRAM
THD TRIM R3 R3 20 k VARIABLE GAIN R4 30 k R1 10 k RECT IN RECTIFIER VREF 1.8 V - OUTPUT + INVERTER IN
R2 20 k G CELL IN
RECT CAP
SR02507
Figure 2. Block diagram
2003 Apr 03
2
Philips Semiconductors
Product data
Compandor
NE570
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC Tamb PD Maximum operating voltage Operating ambient temperature range Power dissipation PARAMETER RATING 24 0 to +70 400 UNITS VDC C mW
AC ELECTRICAL CHARACTERISTICS
VCC = +6 V, Tamb = 25 C; unless otherwise stated. LIMITS SYMBOL VCC ICC IOUT SR PARAMETER Supply voltage Supply current Output current capability Output slew rate Gain cell distortion 2 Untrimmed Trimmed Resistor tolerance Internal reference voltage Output DC shift 3 Expandor output noise Unity gain level5 Gain change 2, 4 Reference drift 4 Resistor drift 4 Tracking error (measured relative to value at unity gain) equals [VO - VO (unity gain)] dB - V2 dB dBm Channel separation NOTES: 1. Input to V1 and V2 grounded. 2. Measured at 0 dBm, 1 kHz. 3. Expandor AC input change from no signal to 0 dBm. 4. Relative to value at Tamb = 25 C. 5. 0 dB = 775 mVRMS. Tamb = 0 C to +70 C Tamb = 0 C to +70 C Tamb = 0 C to +70 C Rectifier input V2 = +6 dBm, V1 = 0 dB V2 = -30dBm, V1 = 0dB - - - 0.2 +0.2 60 - -0.5, +1 - dB dB dB Untrimmed No signal, 15 Hz to 20 kHz 1 No signal TEST CONDITIONS MIN 6 - 20 - - - - 1.7 - - -1 - - - TYP - 3.2 - 0.5 0.3 0.05 5 1.8 20 20 0 0.1 5 +1, -0 MAX 24 4.8 - - 1.0 - 15 1.9 100 45 +1 0.2 10 - UNITS V mA mA V/s % % % V mV V dBm dB mV %
2003 Apr 03
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Philips Semiconductors
Product data
Compandor
NE570
CIRCUIT DESCRIPTION
The NE570 compandor building blocks, as shown in the block diagram, are a full-wave rectifier, a variable gain cell, an operational amplifier and a bias system. The arrangement of these blocks in the IC result in a circuit which can perform well with few external components, yet can be adapted to many diverse applications. The full-wave rectifier rectifies the input current which flows from the rectifier input, to an internal summing node which is biased at VREF. The rectified current is averaged on an external filter capacitor tied to the CRECT terminal, and the average value of the input current controls the gain of the variable gain cell. The gain will thus be proportional to the average value of the input signal for capacitively-coupled voltage inputs as shown in the following equation. Note that for capacitively-coupled inputs there is no offset voltage capable of producing a gain error. The only error will come from the bias current of the rectifier (supplied internally) which is less than 0.1 A. |V IN * V REF | avg GT R1 or | V IN | avg GT R1 The speed with which gain changes to follow changes in input signal levels is determined by the rectifier filter capacitor. A small capacitor will yield rapid response but will not fully filter low frequency signals. Any ripple on the gain control signal will modulate the signal passing through the variable gain cell. In an expander or compressor application, this would lead to third harmonic distortion, so there is a trade-off to be made between fast attack and decay times and distortion. For step changes in amplitude, the change in gain with time is shown by this equation. G(t) + (G initial * G final) e * t t ) G final ; t + 10k C RECT The variable gain cell is a current-in, current-out device with the ratio IOUT/IIN controlled by the rectifier. IIN is the current which flows from the G input to an internal summing node biased at VREF. The following equation applies for capacitively-coupled inputs. The output current, IOUT, is fed to the summing node of the op amp. V IN * V REF V IN + I IN + R2 R2 A compensation scheme built into the G cell compensates for temperature and cancels out odd harmonic distortion. The only distortion which remains is even harmonics, and they exist only because of internal offset voltages. The THD trim terminal provides a means for nulling the internal offsets for low distortion operation. The operational amplifier (which is internally compensated) has the non-inverting input tied to VREF, and the inverting input connected to the G cell output as well as brought out externally. A resistor, R3, is brought out from the summing node and allows compressor or expander gain to be determined only by internal components. The output stage is capable of 20 mA output current. This allows a +13 dBm (3.5 VRMS) output into a 300 load which, with a series resistor and proper transformer, can result in +13 dBm with a 600 output impedance. A bandgap reference provides the reference voltage for all summing nodes, a regulated supply voltage for the rectifier and G cell, and a
bias current for the G cell. The low tempco of this type of reference provides very stable biasing over a wide temperature range. The typical performance characteristics illustration shows the basic input-output transfer curve for basic compressor or expander circuits.
COMPRESSOR INPUT LEVEL OR EXPANDOR OUTPUT LEVEL (dBm) +20 +10 0 -10 -20 -30 -40 -50 -60 -70 -80 -40 -30 -20 -10 0 +10
COMPRESSOR OUTPUT LEVEL OR EXPANDOR INPUT LEVEL (dBm)
SR00677
Figure 3. Basic input-output transfer curve
TYPICAL TEST CIRCUIT
VCC = 15 V
0.1 F 13
10 F
6, 11 20 k 3, 14 2.2 F 20 k G
V1
- +
7, 10 VO
VREF 2, 15 V2 2.2 F 10 k 30 k
4
1, 16 2.2 F
5, 12 8.2 k
8, 9 200 pF
SR02508
Figure 4. Typical Test Circuit
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Philips Semiconductors
Product data
Compandor
NE570
INTRODUCTION
Much interest has been expressed in high performance electronic gain control circuits. For non-critical applications, an integrated circuit operational transconductance amplifier can be used, but when high-performance is required, one has to resort to complex discrete circuitry with many expensive, well-matched components. This paper describes an inexpensive integrated circuit, the NE570 Compandor, which offers a pair of high performance gain control circuits featuring low distortion (<0.1 %), high signal-to-noise ratio (90 dB), and wide dynamic range (110 dB).
BASIC CIRCUIT HOOK-UP AND OPERATION
Figure 6 shows the block diagram of one half of the chip, (there are two identical channels on the IC). The full-wave averaging rectifier provides a gain control current, IG, for the variable gain (G) cell. The output of the G cell is a current which is fed to the summing node of the operational amplifier. Resistors are provided to establish circuit gain and set the output DC bias.
THD_TRIM 8, 9
R3 6, 11 R3 20 k
INV. IN 5, 12
CIRCUIT BACKGROUND
The NE570 Compandor was originally designed to satisfy the requirements of the telephone system. When several telephone channels are multiplexed onto a common line, the resulting signal-to-noise ratio is poor and companding is used to allow a wider dynamic range to be passed through the channel. Figure 5 graphically shows what a compandor can do for the signal-to-noise ratio of a restricted dynamic range channel. The input level range of +20 dB to -80 dB is shown undergoing a 2-to-1 compression where a 2 dB input level change is compressed into a 1 dB output level change by the compressor. The original 100 dB of dynamic range is thus compressed to a 50 dB range for transmission through a restricted dynamic range channel. A complementary expansion on the receiving end restores the original signal levels and reduces the channel noise by as much as 45 dB. The significant circuits in a compressor or expander are the rectifier and the gain control element. The phone system requires a simple full-wave averaging rectifier with good accuracy, since the rectifier accuracy determines the (input) output level tracking accuracy. The gain cell determines the distortion and noise characteristics, and the phone system specifications here are very loose. These specs could have been met with a simple operational transconductance multiplier, or OTA, but the gain of an OTA is proportional to temperature and this is very undesirable. Therefore, a linearized transconductance multiplier was designed which is insensitive to temperature and offers low noise and low distortion performance. These features make the circuit useful in audio and data systems as well as in telecommunications systems.
COMPRESSION G_CELL_IN 3, 14
R2 20 k G
- R4 IG 30 k VREF 1.8 V +
7, 10 OUTPUT
R1 10 k RECT_IN 2, 15
VCC: PIN 13 GND: PIN 4 1, 16 CRECT
SR02509
Figure 6. Chip block diagram (1 of 2 channels) The circuit is intended for use in single power supply systems, so the internal summing nodes must be biased at some voltage above ground. An internal band gap voltage reference provides a very stable, low noise 1.8 V reference denoted VREF. The non-inverting input of the op amp is tied to VREF, and the summing nodes of the rectifier and G cell (located at the right of R1 and R2) have the same potential. The THD_TRIM pin is also at the VREF potential. Figure 7 shows how the circuit is hooked up to realize an expander. The input signal, VIN, is applied to the inputs of both the rectifier and the G cell. When the input signal drops by 6 dB, the gain control current will drop by a factor of 2, and so the gain will drop 6 dB. The output level at VOUT will thus drop 12 dB, giving us the desired 2-to-1 expansion.
R3
*CIN1 EXPANSION
R2 G - VOUT R4 VREF +
VIN OUTPUT LEVEL -20 0 dB NOTES: *CIN2 R1
INPUT LEVEL +20 0 dB
CRECT
SR02510
-40 NOISE -80
-40
GAIN =
2 R3 VIN (Avg.) R1 R2 IB
-80
IB = 140 A
SR00679
* EXTERNAL COMPONENTS
Figure 5. Restricted dynamic range channel
Figure 7. Basic expander
2003 Apr 03
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Philips Semiconductors
Product data
Compandor
NE570
Figure 8 shows the hook-up for a compressor. This is essentially an expander placed in the feedback loop of the op amp. The G cell is set-up to provide AC feedback only, so a separate DC feedback loop is provided by the two RDC and CDC. The values of RDC will determine the DC bias at the output of the op amp. The output will bias to: R DC1 ) R DC2 V OUT DC + 1 ) R4 V REF + 1) R DC TOT 30 k 1.8 V
CIRCUIT DETAILS--RECTIFIER
Figure 9 shows the concept behind the full-wave averaging rectifier. The input current to the summing node of the op amp, VINR1, is supplied by the output of the op amp. If we can mirror the op amp output current into a unipolar current, we will have an ideal rectifier. The output current is averaged by R5, CR, which set the averaging time constant, and then mirrored with a gain of 2 to become IG, the gain control current.
V+ I = VIN/R1 R1 VIN - + R5 10 k CR IG
The output of the expander will bias up to: R3 V V OUT DC + 1 ) R 4 REF V REF + 1) 20 k 30 k 1.8 V + 3.0 V
The output will bias to 3.0 V when the internal resistors are used. External resistors may be placed in series with R3, (which will affect the gain), or in parallel with R4 to raise the DC bias to any desired value.
R2 G
SR02512
Figure 9. Rectifier concept Figure 10 shows the rectifier circuit in more detail. The op amp is a one-stage op amp, biased so that only one output device is on at a time. The non-inverting input, (the base of Q1), which is shown grounded, is actually tied to the internal 1.8 V VREF. The inverting input is tied to the op amp output, (the emitters of Q5 and Q6), and the input summing resistor R1. The single diode between the bases of Q5 and Q6 assures that only one device is on at a time. To detect the output current of the op amp, we simply use the collector currents of the output devices Q5 and Q6. Q6 will conduct when the input swings positive and Q5 conducts when the input swings negative. The collector currents will be in error by the of Q5 or Q6 on negative or positive signal swings, respectively. ICs such as this have typical NPN s of 200 and PNP s of 40. The 's of 0.995 and 0.975 will produce errors of 0.5% on negative swings and 2.5% on positive swings. The 1.5% average of these errors yields a mere 0.13 dB gain error.
V+
R1
*CRECT *RDC *CDC *CIN VIN R4 VREF R3 - *RDC
*CF
VOUT +
SR02511
NOTES: GAIN =
(
R1 R2 IB 2 R3 VIN (avg.)
)
IB = 140 A * EXTERNAL COMPONENTS Q3
Figure 8. Basic compressor
Q7 Q4 Q5 D1 R1 10 k VIN R5 10 k Q6 Q8 Q9
Q1 Q2
I1
I2 CR
NOTE: IG = 2 VIN avg R1
V-
SR02513
Figure 10. Simplified rectifier schematic 2003 Apr 03 6
Philips Semiconductors
Product data
Compandor
NE570
At very low input signal levels the bias current of Q2, (typically 50 nA), will become significant as it must be supplied by Q5. Another low level error can be caused by DC coupling into the rectifier. If an offset voltage exists between the VIN input pin and the base of Q2, an error current of VOS/R1 will be generated. A mere 1 mV of offset will cause an input current of 100 nA, which will produce twice the error of the input bias current. For highest accuracy, the rectifier should be coupled into capacitively. At high input levels the of the PNP Q6 will begin to suffer, and there will be an increasing error until the circuit saturates. Saturation can be avoided by limiting the current into the rectifier input to 250 A. If necessary, an external resistor may be placed in series with R1 to limit the current to this value. Figure 11 shows the rectifier accuracy versys input level at a frequency of 1 kHz.
+1 ERROR GAIN dB
VARIABLE GAIN CELL
Figure 13 is a diagram of the variable gain cell. This is a linearized two-quadrant transconductance multiplier. Q1, Q2 and the op amp provide a predistorted drive signal for the gain control pair, Q3 and Q4. The gain is controlled by IG and a current mirror provides the output current. The op amp maintains the base and collector of Q1 at ground potential (VREF) by controlling the base of Q2. The input current IIN (= VIN/R2) is thus forced to flow through Q1 along with the current I1, so IC1 = I1 + IIN. Since I2 has been set at twice the value of I1, the current through Q2 is: I2 - (I1 + IIN) = I1 - IIN = IC2. The op amp has thus forced a linear current swing between Q1 and Q2 by providing the proper drive to the base of Q2. This drive signal will be linear for small signals, but very non-linear for large signals, since it is compensating for the non-linearity of the differential pair, Q1 and Q2, under large signal conditions.
V+ I1 140 A
0
-1 -40 -20 0 - RECTIFIER INPUT dBm
SR00685
+ R2 20 k VIN Q1 IIN I2 ( = 2 I1 ) 280 A NOTE: IOUT = IG I1 IIN = IG I1 VIN R2 IG Q2 Q3 Q4
Figure 11. Rectifier accuracy At very high frequencies, the response of the rectifier will fall off. The roll-off will be more pronounced at lower input levels due to the increasing amount of gain required to switch between Q5 or Q6 conducting. The rectifier frequency response for input levels of 0 dBm, -20 dBm, and -40 dBm is shown in Figure 12. The response at all three levels is flat to well above the audio range.
V-
SR02514
GAIN ERROR (dB)
INPUT = 0 dBm 0 -20 dBm
Figure 13. Simplified G Cell Schematic The key to the circuit is that this same predistorted drive signal is applied to the gain control pair, Q3 and Q4. When two differential pairs of transistors have the same signal applied, their collector current ratios will be identical regardless of the magnitude of the currents. This gives us: I C1 + I C4 I C3 + I 1 ) I IN I 1 * I IN
3
-40 dBm
10 k
1 MEG FREQUENCY (Hz)
I C2
SR00686
Figure 12. Rectifier frequency response versus input level
plus the relationships IG = IC3 + IC4 and IOUT = IC4 - IC3 will yield the multiplier transfer function, I OUT + IG I1 I IN + V IN I G R2 I1
This equation is linear and temperature-insensitive, but it assumes ideal transistors. If the transistors are not perfectly matched, a parabolic, non-linearity is generated, which results in second harmonic distortion. Figure 14 gives an indication of the magnitude of the distortion caused by a given input level and offset voltage. The distortion is linearly proportional to the magnitude of the offset and the input level. Saturation of the gain cell occurs at a +8dBm level. At a nominal operating level of 0dBm, a 1mV offset will yield 0.34% of second harmonic distortion. Most circuits are somewhat better than this, 2003 Apr 03 7
Philips Semiconductors
Product data
Compandor
NE570
OUTPUT (dBm)
which means our overall offsets are typically about mV. The distortion is not affected by the magnitude of the gain control current, and it does not increase as the gain is changed. This second harmonic distortion could be eliminated by making perfect transistors, but since that would be difficult, we have had to resort to other methods. A trim pin has been provided to allow trimming of the internal offsets to zero, which effectively eliminated second harmonic distortion. Figure 15 shows the simple trim network required.
4 VOS = 5 mV 3 4 mV % THD 2 3 mV 2 mv 1 1 mV 0.34 -6 0 INPUT LEVEL (dBm) +6
At high gains, the signal to noise ratio is 90 dB, and the total dynamic range from maximum signal to minimum noise is 110 dB.
+20
0 MAXIMUM SIGNAL LEVEL 90 dB -40 110 dB
-20
-60
-80 NOISE IN 20 kHz BW -100 -40 -20 VCA GAIN (dB) 0
SR00690 SR00688
Figure 16. Dynamic range Control signal feedthrough is generated in the gain cell by imperfect device matching and mismatches in the current sources, I1 and I2. When no input signal is present, changing IG will cause a small output signal. The distortion trim is effective in nulling out any control signal feedthrough, but in general, the null for minimum feedthrough will be different than the null in distortion. The control signal feedthrough can be trimmed independently of distortion by tying a current source to the G input pin. This effectively trims I1. Figure 17 shows such a trim network.
VCC
Figure 14. G Cell distortion versus offset voltage
VCC
R 3.6 V 6.2 k 20 k To THD Trim 200 pF
R-SELECT FOR
SR00689
3.6 V 470 k 100 k TO PIN 3 OR 14
Figure 15. THD Trim network Figure 16 shows the noise performance of the G cell. The maximum output level before clipping occurs in the gain cell is plotted along with the output noise in a 20 kHz bandwidth. Note that the noise drops as the gain is reduced for the first 20 dB of gain reduction.
SR00691
Figure 17. Control signal feedthrough
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Philips Semiconductors
Product data
Compandor
NE570
OPERATIONAL AMPLIFIER
The main op amp shown in the chip block diagram is equivalent to a 741 with a 1 MHz bandwidth. Figure 18 shows the basic circuit. Split collectors are used in the input pair to reduce gM, so that a small compensation capacitor of just 10 pF may be used. The output stage, although capable of output currents in excess of 20 mA, is biased for a low quiescent current to conserve power. When driving heavy loads, this leads to a small amount of crossover distortion.
RESISTORS
Inspection of the gain equations in Figures 7 and 8 will show that the basic compressor and expander circuit gains may be set entirely by resistor ratios and the internal voltage reference. Thus, any form of resistors that match well would suffice for these simple hook-ups, and absolute accuracy and temperature coefficient would be of no importance. However, as one starts to modify the gain equation with external resistors, the internal resistor accuracy and tempco become very significant. Figure 19 shows the effects of temperature on the diffused resistors which are normally used in integrated circuits, and the ion-implanted resistors which are used in this circuit. Over the critical 0 C to +70 C temperature range, there is a 10-to-1 improvement in drift from a 5% change for the diffused resistors, to a 0.5% change for the implemented resistors. The implanted resistors have another advantage in that they can be made 1/7 the size of the diffused resistors due to the higher resistivity. This saves a significant amount of chip area.
1.15 NORMALIZED RESISTANCE 140 / DIFFUSED RESISTOR
I1
I2 Q6 D1
-IN
Q1
Q2
+IN CC Q5 Q4
OUT D2
Q3
1.10 1 k / LOW TC IMPLANTED RESISTOR
SR02515
1.05
Figure 18. Operational amplifier
1.00
0.95
Figure 19. Resistance versus temperature
2003 Apr 03
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CCCCCC CCCCCC CCCCCC
-40 0 40 80 120 TEMPERATURE
1% ERROR BAND
SR00693
Philips Semiconductors
Product data
Compandor
NE570
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
2003 Apr 03
10
Philips Semiconductors
Product data
Compandor
NE570
REVISION HISTORY
Rev _3 Date 20030403 Description Product data (9397 750 11356). ECN 853-2421 29759 of 03 April 2003. Supersedes data for part-type NE570 included in Product specification NE570/571/SA571 of June 7, 1990. Modifications:
* Remove all data for part types NE571 and SA571.
19900607 19861114 Included in Product specification data sheet NE570/571/SA571. ECN 853-0812 99768. Included in Product specification data sheet NE570/571/SA571. ECN 853-0812 86558.
2003 Apr 03
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Philips Semiconductors
Product data
Compandor
NE570
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 04-03
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 11356
Philips Semiconductors
2003 Apr 03 12

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